The invention relates to a trench cell for storing digital information in a DRAM structure and to a cell array constructed from such trench cells.
DRAM arrays are, typically, realized by a regular configuration of trench cells. For such a purpose, a multiplicity of trench holes is etched into a semiconductor substrate. The lower region of a trench hole, then, serves in each case for accommodating a storage capacitor of the DRAM cell. One or a plurality of selection transistors, embodied as field-effect transistors, is provided per memory cell. The gates of the field-effect transistors can be driven through a word line associated with the cell. Through the source/drain path of the selection transistors, the storage capacitor can be connected to an associated bit line to write digital information to the cell or to read stored values from the cell.
In the course of advancing miniaturization, it becomes more and more important to construct memory cells in a manner that saves as much space as possible. For such a purpose, it is known to integrate the selection transistor or selection transistors of a trench cell into the sidewall of the trench hole. In the case of such vertical selection transistors, the gate electrode of the selection transistor is integrated into the upper part of the trench hole. A thin oxide layer at the sidewall of the trench hole serves as gate oxide. The lower source/drain terminal is formed by a buried doping region, the so-called xe2x80x9cburied strapxe2x80x9d, which is conductively connected to the storage capacitor. A doping region near the surface forms the upper source/drain terminal.
The prior art discloses trench cells for DRAM arrays as a so-called VTC cell concept, in which two vertical selection transistors disposed opposite one another are provided per trench cell. Such a trench cell is shown in FIG. 1. In this cell, the usually weakly p-doped silicon substrate is contact-connected in the necessary manner from the lower substrate region, to be precise, usually from outside the cell array. Because the doping density of the substrate must not be too high, only a contact-connection with relatively low conductivity can be implemented. Furthermore, the problem occurs that the substrate region above the n+-doped buried doping regions can be pinched off from the lower substrate region by the relatively greatly extended space charge zones of the doping regions. This, then, has the effect that the substrate potential for the vertical selection transistors floats freely and erroneous switching states of the transistors arise on account of these fluctuations. In the case of the trench cell shown in FIG. 1, such a pinch-off problem has only been able to be combated hitherto by the cells not being disposed too closely in their spacing from one another. More extensive miniaturization is prevented as a result.
FIG. 2 shows a further trench cell type referred to as a hybrid cell concept. In such a hybrid cell, only one vertical selection transistor is provided per trench cell. In this cell type, too, the substrate is contact-connected from the lower substrate region. The problem with this cell type is that a parasitic transistor can form on the side of the cell opposite to the selection transistor, which has the effect that disturbing leakage currents occur. To prevent these leakage currents from becoming too large, it has always been necessary hitherto to ensure that the cells are not disposed too close together. More extensive miniaturization is prevented as a result.
It is accordingly an object of the invention to provide a trench cell for a DRAM cell array that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that provides a trench cell that enables a densely packed configuration of the trench cells without the process of reading in and out being impaired by leakage currents, and at the same time, enables the semiconductor substrate to be reliably contact-connected.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a trench cell for storing digital information, including a semiconductor substrate of a first conductivity type, the semiconductor substrate defining a trench hole having a lower region, a surface, and an upper region with a sidewall section, a storage capacitor being formed in the semiconductor substrate in the lower region of the trench hole, the storage capacitor having an inner electrode, a dielectric intermediate layer, and an outer electrode, a vertical selection transistor being formed in the semiconductor substrate in the upper region of the trench hole at the sidewall section, the vertical selection transistor having an upper source/drain doping region and a lower source/drain doping region of a second conductivity type, a gate electrode, an insulator layer, and a channel region being disposed between the upper source/drain doping region and the lower source/drain doping region, the channel region being isolated from the gate electrode by the insulator layer, a bit line running in a direction perpendicular to the trench hole, the bit line being connected to the upper source/drain doping region, a word line running perpendicular to the trench hole and transverse with respect to the bit line, the word line being connected to the gate electrode, the lower source/drain doping region being connected to one of the inner and outer electrodes, and a doping region of the first conductivity type being adjacent the surface, the doping region being disposed in the semiconductor substrate opposite the vertical selection transistor viewed in the direction of the bit line adjacent to the sidewall section of the trench hole. In other words, the doping region is disposed adjacent the sidewall section of the trench hole in the semiconductor substrate opposite the vertical selection transistor viewed in the direction of the bit line.
With the objects of the invention in view, there is also provided a cell array, including a multiplicity of regularly disposed trench cells according to the invention.
The invention""s trench cell for storing digital information in a DRAM structure has a vertical selection transistor disposed on thexe2x80x94seen in a bit line directionxe2x80x94first side of the trench hole provided for the trench cell. The upper source/drain terminal of the vertical selection transistor is formed by a doping region situated beside the trench hole and the lower source/drain terminal of the vertical selection transistor is formed by a buried doping region. Both doping regions have a doping of a first conductivity type. The trench cell has a doping region near the surface, of a second conductivity type, on thexe2x80x94seen in the bit line directionxe2x80x94second side adjacent to the trench hole.
The aforesaid leakage current that has been able to cause considerable disturbance to the read-in and read-out behavior of the vertical selection transistors can be, effectively, suppressed by the invention""s doping region near the surface, of the opposite conductivity type to the source/drain doping. This additional blocking doping region is disposed adjacent to a trench sidewall oxide of the cell considered and prevents a parasitic transistor from being able to form at the rear wall of the cell considered. A conductive channel cannot then form between the blocking doping region and the buried source/drain doping region of the selection transistor of the adjacent cell. Independently of the charge of the gate electrode associated with the transistor considered, this prevents a leakage current from being able to form.
In accordance with another feature of the invention, it is advantageous if the blocking doping region extends as far as the substrate surface and is highly doped. This is because the doping implantation can be performed from the substrate surface in such a case. It is furthermore advantageous here if, above the blocking doping region, an interconnect is disposed on the substrate surface, through which the semiconductor substrate can be contact-connected. Through the blocking doping region that extends as far as the silicon surface, the weakly doped substrate of the same conductivity type can be contact-connected through the interconnect. A good contact with the substrate can be produced in this way.
In accordance with a further feature of the invention, the contact with the substrate is produced from the semiconductor surface through an interconnect. Because the conductivity of an interconnect is very much higher than that of the weakly doped substrate, the substrate can be contact-connected significantly better in this way. The substrate potential in the region of the selection transistor can no longer be pinched off even by a widened space charge zone of the buried source/drain doping region (xe2x80x9cburied strapxe2x80x9d) of the selection transistor. As a result, it is always ensured that the substrate potential in the region of the selection transistor has a defined value. Erroneous switching states of the selection transistor can, thus, be prevented. Because consideration is no longer given to the pinch-off effect in the case of the solution according to the invention, the trench cells can be disposed at a shorter distance from one another than hitherto. In this respect, the solution according to the invention makes it possible to increase the storage density.
It is advantageous, moreover, if an insulating layer is disposed above the interconnect and insulates the interconnect from bit lines situated thereabove. The bit line situated thereabove is connected to the highly doped region that functions as upper source/drain terminal of the selection transistor. To insulate the interconnect running above the blocking doping region from the bit line situated thereabove, an oxide layer is disposed between the interconnect and the bit line. The oxide layer must have a thickness such that the distance from the bit line is large enough to keep the contribution to the bit line capacitance as small as possible.
In accordance with an additional feature of the invention, it is advantageous if the interconnect includes polysilicon, tungsten, tungsten silicide, or titanium. First, the materials mentioned have a good conductivity. What is more, the materials are also sufficiently heat-resistant so that the interconnect does not vaporize under the action of heat during subsequent process steps.
In accordance with an added feature of the invention, the first conductivity type is a p-type doping and the second conductivity type is an n-type doping. It is, furthermore, advantageous if the semiconductor substrate and the blocking doping are p-doped because n-channel transistors can, then, be used as selection transistors, n-channel transistors usually having better properties than p-channel transistors. A weakly p-doped well is usually provided in the semiconductor substrate for accommodating the cell array.
In accordance with yet another feature of the invention, the doping concentration of the substrate varies in a manner dependent on the distance from the substrate surface, the doping concentration being minimal at the depth at which the buried source/drain doping region of the selection transistor is situated. The buried source/drain doping region forms, together with the surrounding oppositely doped substrate, a pn junction operated in the reverse direction. The leakage currents of a pn junction increase as the doping density of the substrate increases. To minimize the leakage currents, it is, therefore, advantageous if the doping concentration of the substrate is varied in a manner dependent on the distance from the surface such that it assumes its minimum at the pn junction.
The cell array according to the invention includes a multiplicity of regularly disposed trench cells. When using the trench cells according to the invention, they can be disposed at a short distance from one another so that a high integration density becomes possible.
In accordance with yet a further feature of the invention, the word line is a plurality of word lines, the bit line is a plurality of bit lines, the bit lines and the word lines run orthogonally to one another, and the trench cells are disposed in a rhomboidal configuration at every second crossover point.
It is advantageous, here, if the trench holes are disposed in accordance with a rhomboidal scheme. If a specific bit line is considered, then active word lines and passing word lines alternate along the bit line. The trench cells are in each case situated at the crossover points of the bit line and the active word lines. The active word lines of the bit line considered are, at the same time, the passing word lines of the adjacent bit line. Conversely, the passing word lines of the bit line considered are, at the same time, the active word lines of the adjacent bit line. In the case of the adjacent bit line, too, the trench cells are in each case disposed at the crossover points of the bit line and the active word lines. As such, a rhomboidal scheme is produced for the configuration of the trench holes and makes it possible to accommodate a large number of trench cells per unit area. The word lines and bit lines run orthogonally to one another in the case of this scheme. The invention""s interconnects for contact-connecting the substrate can be integrated into this known rhomboidal scheme. Thus, the scheme does not have to be modified to realize the solution according to the invention.
In accordance with yet an added feature of the invention, the doping region is disposed in the direction of the bit line in a region between the word line associated with a respective one of the trench cells and an adjacent word line running parallel thereto.
In accordance with yet an additional feature of the invention, the word lines have insulating encapsulation, an interconnect is connected to the doping region, and the interconnect is adjacent the surface and is disposed between the insulating encapsulation of a respective one of the word lines associated with a given trench cell and the insulating encapsulation of an adjacent one of the word lines running parallel thereto.
In accordance with again another feature of the invention, an interconnect is connected to the doping region and the interconnect is adjacent the surface and is to be contact-connected from outside the cell array. It is advantageous if the substrate can be contact-connected from outside the cell array through the interconnects. As such, it is not necessary to alter the structure of the word lines and bit lines running orthogonally to one another in the region of the cell array.
Due to the low resistance of the interconnect, a good contact with the substrate can be produced even through a contact-connection of the substrate from outside the cell array.
The fabrication of the trench cells according to the invention proceeds from a pre-patterned semiconductor substrate that already has trench holes with vertical selection transistors each disposed on axe2x80x94seen in a bit line directionxe2x80x94first side of the trench hole. The blocking doping is introduced into each trench hole on the second side opposite the first side seen in the bit line direction.
In such case, the procedure set forth in the following text is preferred when introducing the blocking doping.
Firstly, a doping with doping material of the second conductivity type is introduced in planar fashion onto the semiconductor substrate, between trench holes that are adjacent in the bit line direction. Afterward, the word lines and also the associated insulating encapsulations are patterned, and a doping with doping material of the first conductivity type is, then, introduced in each case into the region between the active word line associated with a trench cell and the passing word line that is adjacent toward the second side of the trench cell, the word lines with their associated insulating encapsulations being used as a mask and the doping being overcompensated with doping atoms of the first conductivity type in the process.
In such a procedure, the first doping may be introduced in planar fashion. In the region in which the second, opposite doping is introduced, the concentration of the second doping material is chosen to be so high that the first doping is overcompensated in the region. As a result, a mask step is necessary only for the introduction of the second doping, while the first doping is introduced in each case without a mask.
During the introduction of the second doping material, the patterned word lines with their insulating encapsulations are in each case used as a mask. Although a mask is necessary for introducing the second doping material, in order to cover parts of the substrate surface, the actual delimitation of the doping regions is prescribed by the insulating encapsulations of the word lines. Due to this effect, referred to as self-alignment, the requirements made of the alignment accuracy and of the production accuracy of the mask can be lowered.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a trench cell for a DRAM cell array, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.